Digital VLSI Design (DVD) - English Lectures

BIU Course Number: 83-612

Lecturer: Prof. Adam Teman

1. Introduction, Digital Design

Section 1a: Introduction

Section 1c: Design Automation

Section 1b: Building a Chip

Section 1d: The Chip Design Flow

Supplementary Material:

Kahoot for Lecture 1

2. Verilog (Synthesizeable RTL)

Section 2a: Verilog

Section 2c: Simple Verilog Examples

Section 2e: Coding Style for RTL – part 1

Section 2b: Verilog Syntax

Section 2d: Verilog FSM Implementation

Supplementary Material:

How to write Synthesizeable RTL

Kahoot for Lecture 2

3. Logic Synthesis - Part I (Standard Cell Libraries)

Section 3a: Logic Synthesis – Part 1

Section 3c: Library Definition

Section 3e: Liberty (.lib)

Section 3b: HDL Compilation

Section 3d: LEF

Section 3f: Contents of Standard Cell Libraries

Supplementary Material:

Kahoot for Lecture 3

Tcl: The Tool Command Language

Intro to Tcl: Part 1

4. Logic Synthesis - Part II (Elaboration and Technology Mapping)

Section 4a: Logic Synthesis – Part 2

Section 4c: Constraint Definition

Section 4e: Verilog for Synthesis – revisited

Section 4b: BDDs and Boolean Minimization

Section 4d: Technology Mapping

Section 4f: Timing Optimization

Supplementary Material:

Kahoot for Lecture 4

5. Static Timing Analysis (STA)

Section 5a: Timing Analysis

Section 5c: Static Timing Analysis (STA)

Section 5e: Design Constraints (SDC)

Section 5g: Timing Reports

Section 5b: Timing Constraints

Section 5d: STA Example

Section 5f: SDC Continued

Section 5h: Multi-Mode Multi-Corner (MMMC)

Supplementary Material:

Kahoot for Lecture 5

6. Moving to the Physical Domain (incl. Floorplan)

Section 6a: Moving to the Physical Domain

Section 6c: Floorplanning

Section 6e: Power Planning

Section 6b: Multiple Voltage Domains

Section 6d: Hierarchical Design

Supplementary Material:

Kahoot for Lecture 6

7. Standard Cell Placement

Section 7a: Standard Cell Placement

Section 7c: Analytic Placement

Section 7e: Placement in Practice

Section 7b: Random Placement

Section 7d: Analytic Placement Example

Supplementary Material:

Kahoot for Lecture 7

8. Clock Tree Synthesis

Section 8a: Clock Tree Synthesis (CTS)

Section 8c: Clock Concurrent Optimization (CCOpt)

Section 8e: Clock Routing and Clock Tree Analysis

Section 8g: Clock Domain Crossing (CDC)

Section 8b: Clock Distribution

Section 8d: Clock Tree Synthesis in EDA Tools

Section 8f: Clock Generation

Supplementary Material:

Kahoot for Lecture 8

9. Gobal and Detailed Routing

Section 9a: Routing

Section 9c: Maze Routing (continued)

Section 9e: Signal Integrity (SI) and Design for Manufacturing (DFM)

Section 9b: Maze Routing

Section 9d: Routing in Practice

Supplementary Material:

Kahoot for Lecture 9

10. Input/Output Circuits and Packaging

Section 10a: Packaging

Section 10c: I/O Circuits – Analog IOs, ESD Protection, Pad Configurations

Section 10b: I/O Circuits – Digital IOs

Section 10d: System-in-Package (SiP)

Supplementary Material:

Kahoot for Lecture 10

11. Chip Finishing and Sign-Off

Section 11a: Sign-off Timing

Section 11c: Chip Finishing, including Density Fill and Antenna Fixes

Section 11b: Additional issues in Sign-off Timing

Section 11d: Sign-off Validation, including IR Drop and EM Analysis, LEC, and DRC/LVS/ERC

Supplementary Material:

Kahoot for Lecture 11

Digital VLSI Design (DVD) - English Lectures

1. Introduction, Digital Design

2. Verilog (Synthesizeable RTL)

3. Logic Synthesis - Part I (Standard Cell Libraries)

4. Logic Synthesis - Part II (Elaboration and Technology Mapping)

5. Static Timing Analysis (STA)

6. Moving to the Physical Domain (incl. Floorplan)

7. Standard Cell Placement

8. Clock Tree Synthesis

9. Gobal and Detailed Routing

10. Input/Output Circuits and Packaging

11. Chip Finishing and Sign-Off

Additional Material: