Short Courses

Advanced Process Nodes

Part 1: Moving to the Third Dimension

Part 3: FinFET Layout

Part 5: Some Current Trends

Part 2: Fabricating FinFETs

Part 4: Layout Dependent Effects and Parasitics

Supplementary Material:

Part 1: Introduction to Digital-on-Top LVS

Part 3: Translating the Verilog netlist into SPICE

Part 5: Running LVS comparison

Part 2: Creating the LVS-ready Verilog Netlist

Part 4: Extracting the LVS-ready Layout netlist

Part 6: Fullchip DRC and Chip Finishing

Supplementary Material:

Custom Block Preparation for Digital-on-Top Integration

Abstract Generation (LEF/LIB) for Custom Blocks (Odem Harel)

Part 1: Introduction

Part 3: The Newton-Raphson Method

Part 5: Other Stuff

Part 2: DC Analysis

Part 4: AC Analysis, Transient Analysis

Supplementary Material:

Part 1: Intro to Tcl

Part 2: Intro to Tcl

Supplementary Material:

TCLPY:
Interfacing Python with your EDA Tools

Udi Kra

Power intent and Low Power Methodology

Supplementary Material:

Intro to DFT (Design for Test)

Supplementary Material:

RISC-V for Embedded Systems: A First Introduction

Supplementary Material: