This was the first BIU analog tapeout. It included thermal sensors, as well as PUF circuits. The circuits exhibited excellent functionality and have generated publications in JSSC, TCAS1, SSCL, and ESSCIRC.
This follow-up tapeout included several new PUF circuits, all of which functioned well in Silicon. Papers were published in CICC and ISCAS 2019. Journal versions of these papers are being prepared at the present time.
stands for Cryptography And Memory EnICS Labs (CAMEL) CHIP. This 65nm chip inhabits testing constructs for more than eight technologies to protect cryptographic implementations against physical Side-Channel-Analysis (SCA) attacks. Namely, protection of digital processing logic and low-lever register-based memories, several of our patents and many papers originated from this test-chip. Quite innovative and advances design techniques were used in the construction of this chip to allow low-noise measurements and security evaluation, including unique power-gated micro-pads access measurement points and advanced utilization of CPF flows. For details contact Dr. Itamar Levi.
stands for Trustworthy Reconfigurable Programmable Logic Array. In principle, originating from the hardware-security group, this unique ASIC incorporats a self-designed 65nm Secured-FPGA against SCA attacks. Specifically, several low-cost breakthrough signal-reduction and noise-insertion technologies are used for protecting the CLBs tailored for this structure. In the CHIP we have three different arrays of ~30×30 CLBs which is fairly large for an academic group test-chip, exhibiting excellent security with minor electronic properties cost. Moreover, we have developed unique automated tools to test, debug, program (i.e. load bitstreams) from functional specifications for the TRPLA. For details contact Dr. Itamar Levi.