BIU Course Number: 83-313
Lecturer: Prof. Adam Teman
Section 1a: Intro to the Intro
Section 1c: How a Chip is Born
Section 1b: The World of Chip Design
Section 2a: A Process Primer
Section 2c: Process Variations
Section 2b: Detailed Process Flow
Section 2d: Manufacturing Issues
Section 3a-3b: MOS Models
Section 3d: Simulating Variation
Section 3c: Threshold Voltage Revisited
Section 3e: Leakage in NanoScaled Transistors
Supplementary Material:
Kahoot for Lecture 3 – Sections a-d
Kahoot for Lecture 3 – Sections e
Section 5a: Moore’s Law
Section 5c: The NanoScaled Transistor
Section 5b: Scaling Models
Section 5d: Current and Future Trends
Section 6a-b: Capacitance
Section 6e: Wire Scaling
Section 6c-d: Resistance and Interconnect Modeling
Section 7a: Sequential Logic – Motivation
Section 7c: Timing Parameters
Section 7e: Basic Timing Constraints
Section 7b: Sequential Logic Elements
Section 7d: Other Flip Flop Implementations
Section 7f: Static Timing Analysis Example
Section 8a: SRAM – Introduction
Section 8c: 6T SRAM Operation
Section 8e: SRAM Stability
Section 8b: The 6T SRAM Bitcell
Section 8d: 6T SRAM Layout
Section 8f: SNM Calculation
Section 9a: SRAM Peripherals – Overview
Section 9c: Column Decoder and Sense Amplifiers
Section 9b: Row Decoder Design
Section 10a: Intro – Basic Addition
Section 10c: Basic Multiplication
Section 10b: Fast Adders
Section 10d: Fast Multipliers
Supplementary Material:
Kahoot for Lecture 10 – Sec a-b
Kahoot for Lecture 10 – Sec c-d
Section 11a: Other Memories
Section 11c: Dynamic RAM (DRAM)
Section 11e: Emerging Memories (PCM, ReRAM, MRAM, FeRAM)
Section 11b: Read Only Memory (ROM)
Section 11d: Non-Volatile Memory (NVM)
EnICS Labs | Bar-Ilan University
The Alexander Kofkin Faculty of Engineering
Building 1102 | floor -1, room 62
Ramat Gan 5290002
Israel