Full RTL2GDS Demo using Cadence Tools

Full flow demonstration using Cadence Xcelium, Genus, Innovus, Voltus, Tempus

Developed and delivered by: Prof. Adam Teman

Complete Playlist on YouTube
Back to all courses

Preface: Project Workspace Overview

Project Workspace Overview

Supplementary Material:

Accompanying Slides

Part 1: Logic Simulation

Part 1: Logic Simulation with Xcelium

Supplementary Material:

Accompanying Slides

Part 2: Simple Block Synthesis

Part 2a: Synthesis with Genus

Part 2b: Synthesis with Genus

Supplementary Material:

Accompanying Slides

Part 3: Gate-level Simulation and Power Estimation

Part 3a: Zero-delay GLS

Part 3b: Backannotation and Power Estimation

Supplementary Material:

Accompanying Slides

Part 4: Place and Route on a simple block

Part 4.1: Getting Started

Part 4.4: Specify Floorplan

Part 4.7: Placement

Part 4.2: Init Design

Part 4.5: Rings and Physical Cells

Part 4.8: CTS

Part 4.3: Global Nets

Part 4.6: Power Grid

Part 4.9: Routing and Signoff

Supplementary Material:

Accompanying Slides

Part 5: Full SoC Example

Part 5.1: SoC Overview

Part 5.4: Moving on to Innovus

Part 5.7: Clock Tree Synthesis

Part 5.2: Running Compilation

Part 5.5: Full Chip Floorplan

Part 5.8: SoC Routing and Timing Reports

Part 5.3: SoC Synthesis

Part 5.6: SoC Placement

Part 5.9: Post-Route and Signoff

Supplementary Material:

Accompanying Slides

Additional Material and Notes:

Note that I have made significant effort to blur and block any and every reference of external IP, beyond the basic features of the EDA tools and open source projects. If you notice any piece of information that is not blocked, please inform me at [email protected] and I will correct this as soon as possible.