English:
Section 2a: Verilog
Section 2b: Verilog Syntax
Section 2c: Simple Verilog Examples
Section 2d: Verilog FSM Implementation
Section 2e: Coding Style for RTL – part 1
Supplementary Material:
How to write Synthesizeable RTL
Kahoot! for discussing Lecture 2
עברית (Slides): Section 2a, 2b, 2c, 2d, 2e
EnICS Labs | Bar-Ilan University
The Alexander Kofkin Faculty of Engineering
Building 1102 | floor -1, room 62
Ramat Gan 5290002
Israel