Digital VLSI Design

מעגלי ומערכות וי.אל.אס.איי. דיגיטליים

Course number:83-612

Course lectures

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Preparation of these recorded
lectures was kindly supported by Intel.

1. Introduction

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DVD – Lecture 1a: Introduction
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DVD – עברית Lec 1a: Introduction
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DVD – עברית Lec 1b: Building a Chip
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DVD – עברית Lec 1c: Design Automation
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DVD – עברית Lec 1d: The Chip Design Flow
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DVD – Lecture 1b: Building a Chip
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DVD – Lecture 1c: Design Automation
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DVD – Lecture 1d: The Chip Design Flow
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DVD – Kahoot for Lecture 1: Introduction

2. Verilog (Synthesizeable RTL)

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DVD – Lecture 2a: Verilog
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DVD – Lecture 2b: Verilog Syntax
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DVD – Lecture 2c: Simple Verilog Examples
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DVD – Lecture 2d: Verilog FSM Implementation
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DVD – Lecture 2e: Coding Style for RTL – part 1
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Supplementary Material – How to write Synthesizeable RTL
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DVD – Kahoot for Lecture 2: Verilog HDL
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DVD – עברית Lec 2a: Verilog
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DVD – עברית Lec 2b: Verilog Syntax
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DVD – עברית Lec 2c: Simple Verilog Examples
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DVD – עברית Lec 2d: Verilog FSM Implementation
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DVD – עברית Lec 2e: Coding Style for RTL – part 1

3. Logic Synthesis - Part I (Standard Cell Libraries)

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DVD – Lecture 3a: Logic Synthesis – Part 1
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DVD – Lecture 3b: HDL Compilation
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DVD – Lecture 3c: Library Definition
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DVD – Lecture 3d: LEF
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DVD – Lecture 3e: Liberty (.lib)
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DVD – Lecture 3f: Contents of Standard Cell Libraries
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DVD – Kahoot for Lecture 3: Logic Synthesis Part 1
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DVD – עברית Lec 3a: Logic Synthesis – Part 1
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DVD – עברית Lec 3b: HDL Compilation
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DVD – עברית Lec 3c: Library Definition
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DVD – עברית Lec 3d: LEF
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DVD – עברית Lec 3e: Liberty (.lib)
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DVD – עברית Lec 3f: Contents of Standard Cell Libraries